1 PC Architecture Book Series
2-1 Signals Used for Different Link Widths
2-2 Maximum Bandwidth Based on Various Speeds and Link Widths
4-1 Control Packets And The HyperTransport Command Types
4-2 HyperTransport NOP Packet Bit Assignments
4-3 HyperTransport Sync Packet Bit Assignments
4-4 HyperTransport Sized Read/Write Packet Bit Assignments
4-5 HyperTransport Broadcast Message Packet Bit Assignments
4-6 HyperTransport Flush Packet Bit Assignments
4-7 HyperTransport Fence Packet Bit Assignments
4-8 HyperTransport Atomic Read � Modify-Write Packet Bit Assignments
4-9 HyperTransport Read Response Packet Bit Assignments
4-10 HyperTransport Target Done Response Packet Bit Assignments
6-1 Summary Of Host Ordering Rules For Transaction Pairs
7-1 Implications Of Sending Information And Request Control Packets
8-1 Contents of the Interrupt Definition Registers
9-1 Summary of Upstream SysMgtCmd Encodings
9-2 Summary of SysMgtCmd Encodings
11-1 Definitions Of Request Packet Fields Used In Routing
11-2 Request Packet Command Code Summary
11-3 Definitions Of Response Packet Fields Used In Routing
12-1 Transmitter Value Driven to Indicate Receiver Width
12-2 Interpretation of Value Received on the CAD Lines to Determine Receiver Width
12-3 Encoded Link-Width Values used in the Link Configuration Registers
12-4 CTL/CAD Sequence Following Deassertion of RESET#
12-5 Encodings for Link Frequency Field of Link Configuration Register
12-6 Signal States During Warm Reset
13-1 HyperTransport Header Command Register Bit Assignment
13-2 HyperTransport Header Status Register Bit Assignment
13-3 HyperTransport Advanced Capability Codes
13-4 Slave Interface Block Command Register Bit Assignment
13-5 Slave Interface Block Link Control Register 0,1 Bit Assignment
13-6 Slave Interface Block Link Configuration Register 0,1 Bit Assignment
13-7 Slave Interface Link Error Registers 0,1
13-8 Slave Interface Link Frequency Capability Registers 0,1
13-9 Slave Interface Feature Capability Register
13-10 Slave Interface Error Handling Register
13-11 Host Interface Block Command Register Bit Assignment
13-12 Host Interface Feature Capability Register
13-13 Revision ID Capability Block Bit Assignment
14-1 Signal Group/Source Synchronous Clock Association
14-2 Differential Pair Power Consumption
14-3 DC Impedance Specification
14-4 Differential DC Output Voltages
14-5 Differential DC Input Voltages
14-6 AC Impedance Specification
14-7 AC Differential AC Output Voltages
14-8 Differential DC Input Voltages
14-9 Differential Input Edge Rate Parameters and Values
14-10 Single-Ended Signaling Characteristics
14-11 Maximum Differential Output and Input Skew Values
14-12 Source Synchronous CLK Output Skew Values
14-13 Source Synchronous CLK Input Skew Values
14-14 Setup and Hold Times for CAD and CTL
15-1 Timing Variance Budget from Specification for Source of Clock Variation
16-1 HyperTransport Bridge Header Command Register Bit Fields
16-2 HyperTransport Bridge Header Status Register Bit Fields
16-3 HyperTransport Bridge Secondary Status Register Bit Fields
16-4 Bridge Memory And Prefetchable Base And Limit Register Bit Fields
16-5 Bridge I/O Base And Limit Register Bit Fields
16-6 HyperTransport Bridge Control Register Bit Fields
17-1 Slave Command CSR: Definitions Of Key Fields In DHC Configuration
17-2 Host Interface Block Host Command CSR Bit Assignment
20-1 PCI Ordering Rules
20-2 PCI to HT Command Conversion
20-3 HT to PCI Command Conversion
20-4 PCI-X Ordering Rules
20-5 PCI-X to HT Command Conversion
20-6 HT-to-PCI-X Command Conversion
20-7 AGP-to-HT Command Conversion
22-1 Summary of Interrupt Request Bit Field Encoding Values
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