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AT AttachmentThe dominant hard disk interface for the computer has become the AT Attachment design梐 natural outcome considering that the interface is based on the ISA expansion bus, at one time the most widely used computer bus. Despite its wide application, you still might never have heard of the AT Attachment name. It goes under more aliases than a candidate for the Ten Most Wanted list. The most familiar of its alternate monikers is IDE, which stands for Integrated Drive Electronics and is a term that correctly describes a technology rather than a specific interface. Nevertheless, the name IDE gets used indiscriminately by people in the computer industry for the AT Attachment design. Sometimes engineers call ATA the AT interface, which strictly speaking it is not. Although engineers created ATA in its original form for low-cost small-capacity drives, it has grown along with the needs of modern computers, keeping in step with the need for both higher capacities and faster access to information. In fact, today's ATA interface can handle more capacity than any disk drive foreseeable in your lifetime. And its speed far exceeds the capabilities of any current disk drive mechanism. But AT Attachment isn't a single interface. During its long evolution since its introduction in 1991 (several preliminary versions were used by products before then and after 1985, when engineers first began work on what eventually became the standard), it has undergone several stages of refinement. Every year or two, a new version of the standard gets approved. The current version is ATA-6, although ATA-7 is already in the works. Table 10.1 briefly summarizes the history of the AT Attachment standard.
PerformanceMuch of the development of ATA has been focused on improving its performance to keep it in step with disk drive and computer technology. The designers of the interface have done an admirable job, not only keeping it ahead of current technology but also pushing far beyond it. Today's hard disk drive mechanisms are limited by physical and design factors to far lower speeds than the ATA interface can deliver. As engineers refined the ATA standard, they increased performance by adding new transfer modes to the operating features of the drive. Each new drive usually supports the fastest mode defined at the time it is made as well as all the older, slower modes. The host computer, its operating system, and the drive negotiate the fastest transfer mode that all understand to use for their transfers. That way, you always get the fastest possible performance from your disk drive. Moreover, even the newest drives can work with old computers (or old drives can work with new computers). The current ATA standard recognizes 11 transfer modes, each with its own performance limit. Table 10.2 summarizes the principal transfer modes of the AT Attachment standard.
AT Attachment supports two broad classes of transfers: Programmed Input/Output (PIO) and Direct Memory Access (DMA). Under the more recent iterations of the ATA standard, DMA is further divided into Single-Word DMA, Multi-Word DMA, and UltraDMA (once called synchronous DMA) modes. With today's computers, UDMA modes are preferred for their higher performance. The difference between PIO and DMA modes is how they use the resources in your computer. The DMA modes provide an opportunity for improved overall system performance through bus-mastering, but the full potential of this benefit requires matching hardware and software in your computer. The fastest modes match only with the most recent computers. Programmed Input/Output puts your microprocessor to work. The microprocessor in your system directly controls every byte that moves through the interface. The microprocessor directly writes values from its registers or memory to a special I/O port, which transfers the data to the control circuitry of the interface. PIO transfers can be of one of two types: blind and flow-control. Blind transfers don't give the AT Attachment drive full control of the transfers. It has no information about the ability of the microprocessor host to accept data. In effect, it is blind to the capabilities of the host. By design, any error the system makes will be on the conservative side to maximize the reliability of the system. Because sometimes only a part of the full bandwidth of your computer is available for making disk transfers, blind transfers throttle back to the worst case. Consequently, AT Attachment operates blind transfers at a slow rate regardless of the host computer's ability to capture the data. It moves bytes at the lower, throttled rate even when 100 percent of the bandwidth is available. Flow-control transfers use a form of handshaking to ensure that disk transfers take advantage of all the available bandwidth. Specifically, controlled transfers use the I/O Channel Ready (IORDY) line in the AT Attachment interface to signal to the computer host when the drive needs to make a high-speed transfer. Using the IORDY line, the drive can call for maximum drive bandwidth support and increase its transfer rate. The current ATA specifications allow for five modes of PIO transfers, as listed in Table 10.3. Modes 0, 1, and 2 use blind transfers. Modes 3 and 4 use flow control.
The AT Attachment standard allows for Direct Memory Access transfers, which in turn allow for bypassing the host computer's microprocessor and moving data directly to memory. But their real speed comes from the reduced cycle times, bursting blocks of data, and bus-mastering. Moreover, when the host operating system does not serialize input/output functions, DMA transfers allow a degree of parallel processing. The host microprocessor can engage in other activities while the DMA transfer progresses. Versions of Windows based on DOS (including Windows 95, 98, and Me) serialize their I/O functions, so they do not gain this benefit. Unix, Windows NT, Windows 2000, and Windows XP can achieve gains from this transfer strategy. AT Attachment allows both single- and multi-word DMA transfers. Single-word DMA transfers move one word at a time. The host sets up the transfer, selects the data to be transferred, and then makes the transfer. The next word repeats the process. The ATA specifications acknowledge three single-word DMA modes, as listed in Table 10.4. But the one-word-at-a-time transfers incur substantial unnecessary overhead, so these modes are classified as obsolete.
Multi-word DMA transfers replace single-word modes under more recent standards, delivering improved performance by operating as a burst mode. After the host sets up the transfer, it selects the starting and ending words for the transfer; then the interface moves the entire block of data from start to end with no further intervention. Table 10.5 lists these ATA multi-word DMA modes.
The UltraDMA modes combine two performance-enhancing technologies. The most straightforward boost comes from quickening the clock or reducing cycle time and taking advantage of bus-mastering technology. By shifting control of the bus to the drive system, the UDMA modes can quicken the pace of transfers. In addition, UltraDMA doubles-up transfers. Normally a DMA transfer is made on one edge of the clock cycle梩ypically on the leading or rising edge when the cycle begins梥o one transfer occurs during each clock tick. An UltraDMA system can transfer data on both the rising and the falling edge of each clock cycle梩hat's two transfers for every clock tick, an effective doubling of throughput. To make this system work reliably, the ATA designers shifted from asynchronous transfers to synchronous transfers. The transmitting device (the computer when writing data; the disk drive when reading) generates the clock and synchronizes the data pulses to the clock. Because one device controls both the clock and the data, it can control them better. In order for the disk drive to take control of the timing, it must act as a bus master, so this technology is sometimes termed bus master DMA. In addition, error protection is built in to the transfer protocol using a cyclical redundancy check (CRC) algorithm. The CRC applies only to the cable transfer, not the data stored on disk. Plain UltraDMA takes advantage of the 16.6MHz clocking speed available in ATA PIO mode 4 but enhances it with double-clocking. Other UltraDMA modes use faster clocks to achieve higher peak data rates. These UltraDMA modes are often referred to by their peak transfer rates, so UltraDMA mode 4 is commonly termed ATA/66 or UDMA/66; mode 5, ATA/100 or UDMA/100; and mode 6, ATA/133 or UDMA/133. Ordinarily you don't have to worry about the transfer mode used by an ATA drive system. Your computer should automatically use the fastest mode available without your intervention梠r knowledge. Addressing and CapacityThe AT Attachment interface can limit the storage you connect to your computer because of limitations in addressing data in various ATA versions. Although a drive may physically be able to store hundreds of gigabytes, that capacity might not be useful because the interface used by the drive does not allow all the bytes to be addressed. In effect, the bytes on the drive beyond the addressing limit imposed by the interface have unlisted numbers, and no amount of begging or cajoling the operator will get you through to them. Addressing limitations have constrained the usable capacity of AT Attachment drives almost since their inception. As the need for greater addressing reach has appeared, designers have added new addressing modes to the ATA standard. The latest move finally pushes the upper limit beyond any currently feasible drive capacity. CHS AddressingWhen engineers first conceived ATA, they based its addressing system on physical attributes of the hard disk the interface was to control. They assigned blocks of storage based on the heads, tracks, and sectors of the disk drive. This addressing system is sometimes called CHS addressing for Cylinder (the techie term for track), Head, Sector addressing. Somewhat arbitrarily, the engineers allowed for addressing disks with 16 separate heads or disk surfaces, each of which may have up to 65,536 tracks spread across it. Each track could contain up to 255 sectors of 512 bytes each梐ll generous figures for the state of technology at the time. Multiply these numbers, and you'll see the that CHS scheme allowed for a capacity limit of 136,902,082,560 bytes or 127.5GB (in the days when a large hard disk measured 40MB). Most people round that capacity number to 128GB, even though it's a bit less, because of the limit of 255 rather than 256 sectors per track. (For historical reasons, drive-makers start numbering sectors with one rather than zero.) The scheme should have worked until the year 2002, when the drive-makers introduced the first 130GB drive, the first to exceed the CHS imposed limit. Unfortunately, in practical application, the BIOSs of older computers severely constrained ATA addressing. All software that relies on interrupt 13(hex) code routines in your computer's BIOS must abide by the BIOS's own disk addressing system. The BIOS routines originally developed in 1982 for the IBM personal computer XT allowed for disks with up to 255 heads or disk surfaces (IBM started number heads with one so the limit is 255 rather than 256), each with up to 1024 tracks on them. Each track can hold up to 63 sectors. This somewhat different geometry allowed for a small total capacity�,422,686,720 bytes or 7.8GB梬hen using standard 512-byte sectors. Most sources round this figure up to 8GB. A problem arises when the two limits of these two geometries get combined. The largest value that the system can handle for any of the three drive parameters is the smaller of the limits set by the two standards. Table 10.6 summarizes the interaction between the BIOS and ATA limits.
The result is that ATA disks that are addressed through the interrupt 13 facilities of the BIOS of a computer cannot address more than 63 sectors per track (the BIOS limit), 16 heads (the ATA limit), and 1024 tracks (the BIOS limit again). With 512-byte sectors, the top capacity is 528,482,304 bytes (about 504MB). Bytes beyond this limit simply cannot be addressed through the standard interrupt 13(hex) routines of the standard computer BIOS. CHS TranslationBecause the AT Attachment design as a system-level interface allows the inner workings of the ATA device to be hidden from your computer, manufacturers are free to alter the geometry of the drive as long as they make it look like something recognizable to your computer. The number of physical heads, tracks, and sectors inside the drive are usually totally different from the number of heads, tracks, and sectors your computer uses to address the sectors on the disk. The drive translates the incoming addresses to its own, internal physical addresses when it seeks out a sector. Engineers broke through the 504MB limit by adding CHS translation to the BIOSs of computers. The BIOS translates commands from your software and operating system to its own CHS addressing system with the 8GB capacity limit. CHS translation is more a band-aid than solution and, thanks to revisions in the ATA specification, is not needed by modern drives (which are larger than the 8GB limit, anyway). Logical Block AddressingThe ATA-2 specification introduced an alternate way of organizing disks called logical block addressing (LBA). It sidesteps the BIOS and substitutes 28-bit logical block addresses for disk sectors. Each sector on the drive is assigned a unique logical address that would be used by the BIOS to reach its contents. The full 28-bit addressing scheme allows for 268,435,456 sectors梐bout 137.5GB. The choice of a 28-bit scheme was essentially arbitrary梚t simply matched the CHS limit well, allowing slightly more capacity. Of course, this scheme was foreign to BIOSs and operating systems. BIOSs written after the development of LBA technology accommodate it by translating LBA addresses into CHS addresses (sound familiar?). Operating systems require drivers to understand the technology (which are included with all modern versions of Windows). Problems with some BIOSs limited the capacity of hard disk that could be addressed (sometimes to as small as 2 or 3GB, but more often to 8GB) because the BIOS translated LBA addresses into CHS addresses with all their limitations. 48-bit AddressingAs the ATA standard bearers, known formally as the ANSI T13 Technical Committee, were preparing the fifth version of their specification, they decided to put to rest capacity limits once and forever梐t least for the foreseeable future. With the ATA-6 specification, they added a new addressing system that accommodated logical block addresses 48 bits long, equivalent to about a million times more on-disk capacity (a total of 144,115,188,075,855,360 bytes). In more convenient language, that's 144 quadrillion bytes, or 144 petabytes (PB). The new addressing scheme uses the same registers as the older 28-bit addressing system. It doubles the width of the registers used for LBA addresses by layering them. (Technically speaking, the registers act as a two-byte First In/First Out buffer.) For example, the operating system first writes the most significant bits of the LBA of a sector and then writes again to load the least significant bits of the LBA. Just adding more bits is not sufficient to make a new addressing system work, of course. The addressing revision also includes new commands to access and use the longer addresses. At the same time, the committee elected to increase the largest possible transfer per command from 256 sectors to 65,536 sectors, allowing new drives to swallow and disgorge up to 32MB with a single command. The ATA system accommodates such large transfers by doubling the width of the sector count register by layering it in the same way as the LBA registers. An operating system that's aware of the ATA-6 specifications can determine whether a drive uses 48-bit addressing using the ATA Identify Device command. For compatibility, all drives with 48-bit addressing also support 28-bit addressing, although only part of their capacity may be available using it. Unfortunately, 48-bit addressing doesn't entirely eliminate addressing limits on disk capacity. It just shifts them back to the operating system. Most operating systems are designed for handling only 32-bit addresses, so most (including most versions of Linux and the entire Windows family) cannot handle capacities larger than 2.19 terabytes (trillion bytes, abbreviated TB). Other FeaturesAlthough speed and capacity issues highlight most discussions of disk interfaces, the AT Attachment standard covers other issues as well. The ATA Packet Interface allows you to connect other devices such as CD and DVD drives to an interface that was originally designed just to handle hard disks. Power management under the ATA rubric makes your computer more energy efficient梐nd lets you keep computing on your notebook computer even after a mixture of fog and pilots lost in the lounge leaves you waiting at the airport gate long after any of your hopes of making your connection have departed. Built-in security features protect you from prying eyes and your data from errant erasures. And the automatic drive-identification capabilities of ATA makes setting up a computer a simpler chore, one that makes lengthy lists of drive parameters as happily behind you as a visit from in-laws who have finally finished an overly prolonged visit. ATA Packet InterfaceAs it was originally conceived, the AT interface lacked facilities to control everything that a CD or DVD drive needed to do, such as play audio and video or simply change disks. It was designed for hard disks that never change and merely absorb and disgorge data. When it comes to ordinary data, however, CD-ROMs are simpler still梩hey only discharge data. To accommodate other kinds of storage media, the T13 committee added the AT Attachment Packet Interface (ATAPI) to the ATA specifications. The committee based the command set on those used by the SCSI system but otherwise kept the scheme completely compatible with existing ATA hardware and drivers. They did not entirely duplicate SCSI, however. Although ATAPI uses many of the same block and command definitions described by SCSI, it does not use many of the other features of SCSI protocol, such as messaging, bus sharing with multiple computers, disconnect/reconnect, and linking and queuing of commands. ATAPI changes nothing on the computer side of the AT connection, and it does not affect the design or operation of ATA hard disk drives. It just gives the makers of other storage devices and programmers guidance as to how to link their products to computers in a standard way. Normally, an ATA hard disk gets its commands through eight registers called the Task File, which passes along all the commands and parameters needed to operate the disk. Unfortunately, these eight registers are not sufficient for the needed CD or DVD control. ATAPI adds one new command, the Packet Command, that initiates a mode in which multiple writes to the Task File will send packets of commands to the CD or DVD drive. Most ATAPI command packets contain 12 bytes, although the standard also defines 16-byte packets for compatibility with future devices. The first of the 12 bytes in the ATAPI Command Packet (byte 0) is an operation code that defines the command itself. The initial ATAPI specification defined 29 operation codes. The third through sixth byte (bytes 2�) of each packet hold the logical block address of the data to be used if the command involves the use of data. The logical addresses start with zero as the first block and increase sequentially up to the last block. The eight and ninth bytes (bytes 7 and 8) of the packet define the length of the transfer, parameter list, or allocation involved in the command. Special extended commands add an extra byte for indicating this length. The remaining bytes in the packet were not originally defined but are left reserved for future implementations. Power ManagementIn computers where electrical consumption is a critical issue (for example, battery powered notebook machines), the hard disk is one of the major drains of power. Most disk drives meant for portable machines help conserve power by allowing their electrical use to be trimmed when the drive's fastest response is unnecessary. The T13 committee added power-management commands to the specification starting with ATA-3. This design adds four power modes, which allow frugal computers to economize as the occasions arise:
Table 10.7 summarizes and distinguishes the four power-management modes of the ATA specification.
AT Attachment drives with the power-management option also include a built-in standby timer that can shift the drive into its lower-power standby mode after the drive has been inactive for a preset period. This changeover is a function of the drive and occurs automatically without the intervention of the host computer. The host computer can, however, switch off the standby timer so that the drive does not shift to standby automatically. The host computer can then take full command of the power mode of the drive. To switch the drive from active mode to a lower-power mode, the host computer sends the drive a power-management command. Any drive-access command automatically forces the drive back into active mode. In addition, the AT Attachment standard includes a Check Power Mode command that allows the host computer at any time to determine in which mode the drive is currently operating. SecurityStarting with ATA-3, the T13 committee added device-level password security to limit access to disk storage. Although you set the ATA drive access password through your computer, the drive stores the password on its own media and it uses the same password, even if you unplug the drive from one computer and attach it to another. Consequently, if you activate its password security system and someone later steals your drive, this person cannot access the data stored on the drive. Depending on the secrecy of your data, you can set security to one of two levels: normal or maximum. The chief ramification of your choice is what happens should you forget your password. Choose normal security, and the drive-maker can recover your data for you. When you set your drive for maximum security, even the drive-maker cannot retrieve your data. The AT Attachment standard allows for two kinds of passwords:
Under the ATA security system, your drive operates in one of three modes:
Device IdentificationEach device includes 512 bytes of storage for identifying information. Device-makers are free to locate this storage anywhere they want. It can be stored on a nonremovable storage medium, such as a hard disk, or in EEPROM or Flash memory. Regardless of its location, the AT Attachment standard includes a standard command for reading this identifying block. Using this command, your computer can interrogate the device to find out what it is and automatically configure itself for optimum operation, including maximizing its data-transfer rate. Included are the device parameters, the features supported (including transfer modes and thus speeds), the model number, and the serial number of the drive. Logical InterfaceThe AT Attachment interface logically links to the rest of your computer through a series of registers. The standard does not constrain the port addresses used by these registers. Their location is set by the BIOS writer and chipset designer of your computer. The registers are generally inside the motherboard chipset, and the BIOS must be written to match. Add-in host adapters include their own registers and matching add-on BIOS. Applications and operating systems that use the BIOS never need know the location of these ports. Software drivers for operating systems that bypass the BIOS must be written with the proper register addresses. Most chipset-makers use the same range of addresses for the I/O ports used in communicating with their AT Attachment interfaces. Consequently, a single set of register addresses has become a de facto standard in nearly all computers. Table 10.8 lists these register addresses.
A single ATA connection is meant to handle the control of two drives. Most modern host adapters include a secondary port梐nother connector to plug in a cable for two more ATA devices. The logical location of the ports used by both the primary and secondary AT Attachment host adapters is not fixed and can be set at any of several ranges of values that the hardware manufacturer chooses. The chosen I/O port addresses only need to be reflected in the BIOS routines for interrupt 13(hex) service and the software drivers used to control the board. Nevertheless, most manufacturers use the same ports and interrupts for their primary and secondary AT Attachment ports. Signals and OperationThe hardware side of the AT Attachment interface is based on the Industry Standard Architecture (ISA) bus, but it is not the complete bus. For example, hard disk drives are not normally memory-mapped devices, so there's no need to give a hard disk control of the addressing signals (24 of them) of the ISA bus. Instead, the registers of the interface connect to the input/output address space of the ISA bus, and only those signals used in addressing the ATA registers need to be used. In addition, AT Attachment uses a 16-bit data bus (although it allows for drives that only use eight) as well as a variety of control signals. These include signals to request reading or writing data, to make DMA transfers, to check the results of running diagnostics, and to indicate which of the two drives that can be connected to an AT interface port is to perform a given function. ATA also allows for a "spindle sync" signal so that two drives can spin synchronously, as is required for some implementations of drive arrays. ConnectorsAn AT Attachment interface uses any of three connectors for its interface. The most com mon has 40 pins to accommodate its addressing, data, and control signals. As shown in Figure 10.1, one pin is sometime removed and the connector shell is notched. The connector has a tab corresponding to the notch. Together the tab/notch and missing pin key the connector against improper insertion. Figure 10.1. The 40-pin ATA connector.The 44-pin connector used by 2.5-inch drives adds the three essential power connections as well as a coding pin. A 50-pin connector additionally allows four vendor-unique pin assignments, which are typically used for indicating master or slave status for a given drive. (Two pin spaces are skipped.) Figure 10.2 shows how the power and vendor-unique pins are arrayed on a 50-pin connector. Figure 10.2. The 50-pin ATA connector (of which the 44-pin connector is a subset).Regardless of the connector used by a drive, the function assigned each pin remains the same. Table 10.9 lists the signal assignments of the interface.
ATA drives that are built in to PC Cards or CardBus cards use the 68-pin connection of the associated PCMCIA standards. These are essentially bus connections and are covered in Chapter 9, "Expansion Buses." SignalsSeven of the connections of the AT Attachment interface (numbers 2, 19, 22, 24, 26, 30, and 40) are grounds, scattered among the signals to provide some degree of isolation of one signal from another. Sixteen pins (3 through 18) are devoted to ATA's 16-bit data bus. Beside the 16-bit connection system used by all of today's devices, the AT Attachment specification allows for eight-bit connections through the interface. Such narrow-bus systems use only the odd numbered eight pins in the standard sequence. The remaining 16 pins of the standard 40-pin connector are assigned various signal-control functions, such as those to manage reading or writing data, make DMA transfers, and coordinate the operation of two drives. The AT Attachment signals primarily concerned with controlling the transfer of data across the interface are given their own dedicated connections. Commands to the drives and the responses from the drives (including error indications) are passed through 17 eight-bit registers. The two drives permitted under the AT Attachment standard share the connection and receive all signals across the interface indiscriminately. To signal which drive should act on a given command, the AT Attachment uses a special control register. The same register also determines the head, track, and sector that is to be used at any given time. Seven signals are used to select among the registers. The registers are divided into two groups: Control Block Registers and Command Registers, indicated by two interface signals. Activating the Drive Chip Select 0 signal (pin 37) selects the Control Block registers. Activating the Drive Chip Select 1 signal (pin 38) selects the Command Block Registers. When the Drive I/O Write signal (pin 23) is active, the registers that accept commands from the host are accessible through the interface data lines. When the Drive I/O Read signal (pin 25) is active, the registers indicate drive status through the data lines. Drive Address Bus 0 through 2 are located on pins 35, 33, and 36 and control which register is currently selected and accessible through the data lines. The AT Attachment standard defines two read and one write control-block registers as well as seven read and seven write command-block registers. Of these, one write command-block register selects the active drive and head (up to 16 heads are allowed). Two registers select the drive track (allowing up to 65,536 tracks on a single drive), another register selects the sector to start reading from or writing to, and another register selects the number of the track to be read or written. The read registers indicate which drive and head are active and which track and head are being scanned. Other registers provide status information and define errors that occur during drive operation. The number of register bits available sets the logical limits on device size: up to 16 heads, 65,536 tracks, and 256 sectors per track. Because many computers are incapable of handling more than 1024 tracks, the maximum practical capacity of an AT Attachment drive is 2,147,483,648 bytes (2GB). During active data transfers, separate signals are used as strobes to indicate that the data going to or coming from the drive or values in the control registers are valid and can be used. The falling edge of the Drive I/O Read signal (pin 25) indicates to the host that valid data read from the disk is on the bus. The falling edge of the Drive I/O Write signal (pin 23) indicates that data on the bus to be written on-disk is valid. The Drive 16-bit I/O signal (pin 32) indicates whether the read or write transfer comprises 8 or 16 bits. The signal is active to indicate 16-bit transfers. Normally, AT Attachment transfers are accomplished through programmed I/O, the standard mode of operation using the standard AT hard disk BIOS. However, the AT Attachment standard optionally supports Direct Memory Access (DMA) transfers. Two signals control handshaking during DMA data moves. The drive signals that it is ready to read data and transfer it in DMA mode by asserting the DMA Request signal (pin 21). The computer host acknowledges that it is ready to accept that data with the DMA Acknowledge signal (pin 29). If the host cannot accept all the data at once, it removes the DMA Acknowledge signal until it is ready to receive more. In DMA write operations, the host computer uses DMA Acknowledge to indicate that it has data available, and the active drive uses DMA Request for handshaking to control the flow of data. The Drive I/O Read and Write signals indicate in which direction the data should flow (as a disk read or write). An AT Attachment disk drive can interrupt the host computer to gain immediate attention by activating the Drive Interrupt signal (pin 31). On programmed I/O transfers, the drive generates an interrupt at the beginning of each block of data (typically a sector) to be transferred. On DMA transfers, the interrupt is used only to indicate that the command has been completed. (The interrupt used is determined by the host's circuitry.) A drive can signal to the host computer that it is not ready to process a read or write request using the I/O Channel Ready signal (pin 27). Normally, this signal is activated; the drive switches it off when it cannot immediately respond to a request to transfer data. The Drive Reset signal (pin 1) causes the drive to return to its normal power-on state, ignoring transfers in progress and losing the contents of its registers (returning them to their default values). Normally, the drive is activated briefly (for at least 25 microseconds) when the host computer is turned on so that it will initialize itself. Activating this signal thereafter will cancel the command in progress and reinitialize the drive. The Passed Diagnostics signal (pin 34) is used by the slave drive to indicate to its host that it is running its diagnostics. The Passed part of the name does not mean that the diagnostics are completed successfully but that the results are ready to be passed along to the host system. Actual results (and the command to actually execute diagnostics) are given through the AT Attachment registers. The Spindle Sync/Cable Select signal (pin 28) can be used at the drive manufacturer's option to make the drives spin synchronously (as is required by some drive-array technologies) or to set drive identification as master or slave by the cable rather than using a jumper or switch on the drive. When used as a spindle-synchronizing signal, the master drive generates a periodic pulse (typically once each revolution of the disk, although the actual timing is left to the drive manufacturer), and the slave uses this signal to lock its spin to the master. When this connection is used as a cable-select signal, supplying a ground on pin 28 causes a drive to function as the master (drive 0); leaving the connection open causes the connected drive to act as the slave (drive 1). A single signal, termed Drive Active/Drive 1 Present, located on pin 39, indicates that one of the drives is active (for example, to illuminate the drive activity indicator on the system front panel). The same pin is used by the host signal to determine whether one or two AT Attachment drives are installed when the power is switched on. The drive assigned as the slave is given a 400-millisecond period during system startup to put a signal on this pin to indicate its availability; after waiting 450 milliseconds to give the slave drive time to signal, the master drive puts its signal on the pin to indicate its presence to the host computer. It switches its signal off and converts the function of the signal to drive activity when the drive accepts its first command from the host computer or after waiting 31 seconds, whichever comes first. CompatibilityAs a general rule, all ATA drives support the standard under which they were made as well as all earlier versions of the ATA standard. That is, you can plug the most recent ATA drive into the ATA connector of a vintage computer and have reasonable expectations that it will work. Similarly, you can blow the cobwebs out of drives that conform to earlier ATA standards, plug one into the newest computer, and have it work. (You may have to manually configure your system to accept an old drive by entering parameters into its setup program.) Plugging a fast drive into a slow system yields a slow drive, however. The interface is not magic and is constrained by the oldest technology in the system. Plug the latest ATA/133 drive into a old computer and you may get a drive the works only in PIO modes. Worse, if your system doesn't recognize logical block addressing, only a fraction of the total capacity of the drive may be accessible. In general, you can mix drives with different speed ratings on a single cable. Because ATA handles each transaction individually, the drives should operate at the highest speed at which they are individually capable in the given system. WiringTwo different cables are used by the AT Attachment interface. The basic cable is a flat ribbon with 40 conductors and three connectors, all the same. The typical cable puts two connectors close together at one end and a single connector at the other. Sometimes a computer-maker "cheaps out" and only puts two connectors on the cable, so you can connect only one drive (the other end plugs into your motherboard or a host adapter). The chief problem with the cable design is that it works only for speeds up to 33MHz (that is, ATA/33 or UDMA/33). Higher-speed transfer modes require a more sophisticated 80-conductor cable. The signals in the cable are essentially the same, but every other conductor in the cable is held at ground potential. That way, there is always a ground between two active signals on the cable. The ground effectively shields the two active signals from one another. The ground wires are all linked together in the cable connector. ATA/66 and above interfaces can sense this cable. If they do not find it, they will restrict the transfer speed to 33MHz or less, regardless of the capabilities of the drives you install. Figure 10.3 illustrates the difference between the two cable types. Figure 10.3. ATA connections for speeds greater than 33MHz require 80-conductor cables (left) instead of the 40-conductor cables (right) that suffice for 33MHz and slower speeds.All connectors on an ATA cable are supposed to be keyed (with a missing pin 20) and on the shell of the connectors. In addition, the ATA cable is marked with a red or blue stripe on the edge corresponding to pin 1 on the connector. Single DriveAll three connectors on an ATA cable are the same, so in theory you should be able to plug any connector into any drive or the host adapter. That's not the best practice, however. Convenience dictates that you plug the connector spaced farthest from the rest at one end of the cable into your host adapter. Use the two more closely spaced connectors for disk drives. In a one-drive system, plug the connector at the other end of the cable into the drive and leave the middle connector unconnected. This properly terminates the cable. Otherwise, a fraction of the signal travels down the loose stub and reflects off the unterminated end. The reflected signal travels back and mixes with the signal at the middle drive connector. Because of the time it takes the signal to travel back and forth through the stub, the reflected signal is not a mirror image of the signal at the connector. The signal at the connector will have changed during the travel time. As a result, the combination of the new and reflected signals will be something unpredictable. Figure 10.4 shows how to terminate a single drive properly. Figure 10.4. Recommended wiring of a single AT Attachment drive.Two DrivesConnecting two drives to an AT Attachment cable eliminates the electrical concerns. One drive necessarily will be at the end of the cable and terminate it properly. It doesn't matter which drive connects to which connector梞aster or slave, big or small, old or new. The connectors are electrically identical. Three or Four DrivesMost AT interface host adapters enable you to connect more than two drives by providing two distinct interfaces: primary and secondary. Some systems insist you use the primary connection for the drive that boots your computer. Others are more flexible. In any case, treat both the primary and secondary as an individual ATA interface with its own cable. Always use the last connectors on the cable first, then the connector in the middle of the cable for the second drive. Most dual-interface systems will allow you to connect a single drive to each interface梩wo drives, two cables, two interfaces. Master/Slave DesignationThe AT Attachment system distinguishes the two drives attached to a single cable by making one the master and the other the slave. The chief distinction is, as a default, the master gets assigned a drive letter first (it gets the letter closer to the front of the alphabet), and the master is usually preferred as the boot drive (although many BIOSs will let you select which drive to boot your system). All AT Attachment drives have the potential for being masters or slaves. The function of each drive is determined by jumper settings on the drive. These are usually called drive select jumpers or simply indicated with DS near the contact on the drive's electronic circuit board. Different manufacturers use various designation schemes. A jumper on the pins marked with the "DS," for example, indicates a master. Other manufacturers might use position-sensitive system. A jumper in one position indicates the drive will act as the master, and the jumper in another position indicates it will be a slave. Most drives have a cable select setting, although few computer-makers implement this feature (by which the cable does, in fact, indicate whether the drive is master or slave). Only one master and one slave are permitted in a single AT Attachment connection, so each of the two drives in a single AT Attachment chain must have its master/slave jumpers properly set for the system to work. Moreover, most computers will not boot with only a slave drive. Most drives are shipped "jumpered" for operation as the master, so you only have to adjust the second AT Attachment drive you add to your computer梑ut be sure to check. Sanctioning OrganizationThe ATA standards are published and maintained by the American National Standards Institute, Inc., 11 West 42nd Street, New York, New York, 10036. The more recent versions of the ATA standards have been prepared by the T13 technical committee of Accredited Standards Committee NCITS. The committee maintains a Web site that publishes the working documents and drafts of prospective standards at www.t13.org. The final approved standards are available in final form only from ANSI. |
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