Introduction to Link Power Management

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Introduction to Link Power Management PCI-PM compatible software places devices into one of four states as described in previous sections. PCI Express defines link power management that relates to each of the four device states. Table 16-16 on page 607 lists the Device states (D-States) and the associated Link states (L-states) permitted by the specification. Each relationship is described below: D0 � When a device is in the D0 state is it fully powered and fully functional and the link is typically active (e.g. in the L0 state). PCI Express devices are required to support Active State Power Management (ASPM) that permits link power conservation even when the device is in the D0 state. Two low-power states are defined: L0 standby, or L0s (required) L1 ASPM (optional) Both of these states are managed autonomously by hardware and completely invisible to software. A critical element associated with ASPM is returning to the L0 state with very short latencies. Additional configuration registers permit software to calculate the worst case latencies to determine if ASPM will violate latency requirements of the transactions. D1 & D2 � When software places a device into either the D1 or D2 state the link is required to transition to the L1 state. The downstream component signals the port in the upstream device (root or switch) to which it attaches, to enter the L1 state. During L1 the reference clock and power remain active. D3hot � When software places a device into the D3 state, the device signals a transition to L1 just as done in the D1 and D2 states. However, because the device is in the D3hot state software may choose to remove the reference clock and power from the device called D3cold. Prior to removing the clock and power, software initiates a handshake process that places a device into the L2/L3 Ready state (i.e., power and clock still on, but ready for power to be removed) D3cold � This state indicates that the clock and power have been removed. However, auxiliary (AUX) Power may remain available after the main power rails are powered down. In this case, the link state is referred to as L2. When main power is removed and no AUX power is available it is referred to as L3. Table 16-16. Relationship Between Device and Link Power States Table 16-17 on page 608 provides additional information regarding the Link power states. Table 16-17. Link Power State Characteristics * The L1 state is entered due to PM software placing a device into the D1, D2, or D3 states or optionally L1 is entered autonomously under hardware control when Active State Power Management is supported for L1. ** The specification describes the L2 state as being software directed. The other L-states in the table are listed as software directed because software initiates the transition into these states. For example, when software initiating a device power state change to D1, D2, or D3 devices must respond by entering the L1 state. Software also causes the transition to the L2/L3 Ready state by initiating a PME_Turn_Off message. Finally, software also initiates the removal of power from a device after the device has transitioned to the L2/L3 Ready state. This results in a transition to either the L2 or L3 pseudo-states (so called because power is removed from the devices and actual link state transitions do not apply). Because Vaux power is available in L2, a wakeup event can be signaled causing software to be notified.

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